DIR-V: India’s Indigenous Microprocessor Programme

1.1 What is a microprocessor?

A microprocessor is the chip that runs a device’s instructions. That plain gloss is our own. PIB says microprocessors are the brains of modern electronic devices.

PIB lists mobiles, computers, automobiles, medical equipment, defence systems and satellites as examples. So whoever designs these chips shapes a very large part of modern life.

1.2 What is RISC-V, and why does it matter?

Every processor follows a fixed list of basic commands. That list is called an instruction set. RISC-V is one such list.

PIB says RISC-V is an open architecture that provides a set of instructions for chip design. It says RISC-V involves no licence costs. That allows wider adoption by industry, start-ups and research institutions.

PIB’s 2022 release adds a contrast. It describes ARM and x86 as instruction set architectures, one of which is licensed and the other sold. It says RISC-V has no licensing encumbrances.

1.3 Why does the scale of India's demand matter?

PIB says India consumes around 20% of all the microprocessors manufactured globally. It also says India already has 20% of the world’s chip design engineers.

PIB links these facts to self-reliance. It says owning core processor technology reduces reliance on foreign suppliers. It adds that the aim is to support the growing electronics and digital economy.

2.1 What is the DIR-V Programme?

DIR-V stands for Digital India RISC-V. PIB’s release of 27 April 2022 says Shri Rajeev Chandrasekhar announced the DIR-V Program that day.

Its overall aim was to enable creation of microprocessors for the future in India. It also set a target of industry-grade silicon and design wins by December 2023.

PIB’s 2025 backgrounder says the programme was launched in April 2022. It says the programme brings researchers, startups and industry into a shared design ecosystem.

2.2 Who does what?

PIB’s 2025 backgrounder names the roles.

• MeitY (the Ministry of Electronics and Information Technology) guides programmes through policy support, funding and long-term planning.
• C-DAC (the Centre for Development of Advanced Computing) leads the design of India’s indigenous processors. It creates processor IP, SoCs, development boards and tools.
• Prof. V. Kamakoti, Director of IIT Madras, was announced as Chief Architect of the DIR-V Program in 2022.
• S. Krishnakumar Rao was announced as Program Manager.

An SoC is a system on a chip. That means one chip holding the processor and its supporting parts. This gloss is our own.

2.3 Is DIR-V the same as the Microprocessor Development Programme?

No. PIB lists them as separate MeitY schemes, together with C2S and the India Semiconductor Mission. C-DAC’s VEGA site says the Microprocessor Development Programme was initiated and funded by MeitY.

PIB says C-DAC developed DHRUV64 under the Microprocessor Development Programme. PIB also calls DHRUV64 the third chip fabricated under DIR-V. So one chip sits under both names.

3.1 What are the three chips?

PIB says DHRUV64 is the third chip fabricated under DIR-V. The first is THEJAS32. The second is THEJAS64.

The table covers only what the sources state. PIB lists THEJAS64 as a 2025 chip. SoC means system on a chip.

3.2 Why do Mohali and Chandigarh both appear?

PIB’s backgrounder says THEJAS64 was manufactured at Semiconductor Lab (SCL) Mohali. C-DAC’s release and MeitY’s annual report both say SCL, Chandigarh.

The sources give two place names for the THEJAS64 fab. This lesson reports each as its source wrote it and does not choose between them.

3.3 What does 'made at' mean for a chip?

Designing a chip and making it are different jobs. A design is a plan. A fabrication plant, or fab, turns the plan into real silicon. This gloss is our own.

PIB says India already has deep capabilities in chip design. It says the new semiconductor units will build capabilities in chip fabrication.

4.1 What happened, and when?

Dates below are as the sources give them. Read each line as a dated snapshot.

• December 2021: PIB says the India Semiconductor Mission was launched under MeitY. A February 2024 Cabinet release says the programme was notified on 21.12.2021 with a total outlay of Rs 76,000 crore.
• 27 April 2022: Shri Rajeev Chandrasekhar announces the DIR-V Program (PIB).
• 11 January 2025: C-DAC announces the successful fabrication of THEJAS64 at SCL, Chandigarh. It also launches VEGA-based development boards.
• 11 February 2025: IIT Madras and ISRO announce that the SHAKTI-based IRIS chip was developed and successfully booted.
• 2 September 2025: PIB reports that the first set of Made-in-India chips from a pilot line was presented to the Prime Minister.
• 15 December 2025: PIB posts its backgrounder on DHRUV64. The Register says C-DAC revealed the chip on a Monday, which was that day.
• 28 February 2026: The Prime Minister inaugurates Micron’s ATMP facility at Sanand, Gujarat (PIB).
• 4 July 2026: PIB reports the inauguration of the CG Semi OSAT facility at Sanand.
• 1-2 August 2026: IIT Madras says it will host the third DIR-V Symposium.

4.2 Which date should you remember for DHRUV64?

PIB’s backgrounder carries the date 15 December 2025. Some reports of the launch give other days. This lesson uses the date on the PIB page.

No release we read names a minister or a ceremony for the DHRUV64 reveal. So the lesson does not name one.

5.1 What is DHRUV64?

PIB calls DHRUV64 India’s first homegrown 1.0 GHz, 64-bit dual-core microprocessor. It says C-DAC developed it under the Microprocessor Development Programme.

MeitY’s annual report calls it the third chip based on the VEGA series of indigenous RISC-V processors. It says the SoC was designed, developed and validated entirely in India.

5.2 What is inside the chip?

MeitY’s annual report says the SoC integrates the VEGA AS2161, a 16-stage out-of-order dual-core processor. It says the chip supports single and double precision floating point instructions.

The same report says it has an MMU suitable for Linux-based applications. An MMU is a memory management unit. That gloss is our own.

The Register says DHRUV64 is built on a 28nm process node and can boot Linux. PIB’s chart also labels DHRUV64 as 28nm.

5.3 What do the VEGA names mean?

C-DAC’s VEGA site lists seven variants. The table shows five of them.

The table leaves out the variants ET1037 and AT1051. MeitY’s report calls AS2161 16-stage, while C-DAC’s site gives 13-16 stages for the family. THEJAS32 uses the ET1031 core.

Out-of-order means a processor can run later instructions while it waits for a slow one. That gloss is our own.

5.4 Where can DHRUV64 be used?

PIB says it suits 5G infrastructure, automotive systems, consumer electronics, industrial automation and the Internet of Things. MeitY’s report names industrial automation, networking, medical electronics and consumer electronics.

5.5 What comes next?

PIB says the next processors, Dhanush and Dhanush+, are under development. Their SoC variants are DHANUSH64 and DHANUSH64+.

PIB’s chart gives DHANUSH as 1.2 GHz, quad-core, 28nm. It gives DHANUSH+ as 2 GHz, quad-core, 16/14nm. The Register reports the same figures. Treat them as plans, not delivered chips.

6.1 What is SHAKTI?

The SHAKTI project says SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT Madras. It says the project is building a family of 6 processors on the RISC-V ISA.

PIB’s 2025 backgrounder lists SHAKTI (2018, IIT Madras) as designed for strategic, space and defence applications. A March 2025 PIB release calls SHAKTI India’s first indigenous microprocessor.

6.2 How was the IRIS chip made?

IIT Madras and ISRO announced on 11 February 2025 that they had developed and booted the IRIS chip. IRIS stands for Indigenous RISCV Controller for Space Applications. The press release says it was developed from the SHAKTI baseline.

ISRO’s Inertial Systems Unit in Thiruvananthapuram proposed the idea of a 64-bit RISC-V controller. It worked with IIT Madras on the specifications and design.

• IIT Madras designed and implemented the chip.
• SCL, Chandigarh manufactured it, using SCL’s 180 nm technology node.
• Tata Advanced Systems packaged it at Perjenahalli, Karnataka.
• Prof. Kamakoti said it was the third SHAKTI chip fabricated at SCL Chandigarh, after RIMO in 2018 and MOUSHIK in 2020.

6.3 Which other processors does PIB name?

PIB’s backgrounder lists these examples before DHRUV64.

• SHAKTI (2018, IIT Madras): strategic, space and defence applications.
• AJIT (2018, IIT Bombay): industrial and robotics applications.
• VIKRAM (2025, ISRO-SCL): space applications such as navigation, guidance and mission operations.
• THEJAS64 (2025, C-DAC): industrial automation.

6.4 Is SHAKTI separate from DIR-V?

Not in the way older notes say. PIB’s 2022 release shows a DIR-V roadmap with SHAKTI by IIT Madras and VEGA by C-DAC. IIT Madras says SHAKTI is backed by MeitY under its Digital India RISC-V initiative.

The three chips in this lesson are the VEGA line from C-DAC. SHAKTI is a different processor family from a different institution. Both sit inside the wider DIR-V effort.

7.1 What is the India Semiconductor Mission?

PIB says the India Semiconductor Mission (ISM) was launched in December 2021 under MeitY. PIB’s 2025 backgrounder says it works with global companies to bring large semiconductor investments into the country.

As of 2025, PIB says the mission had approved ten projects across six states. It gives the total investment commitment as Rs 1.60 lakh crore.

A February 2024 Cabinet release makes the split plain. It says India already has deep capabilities in chip design. It says the new units will build capabilities in chip fabrication.

7.2 Which units does PIB name?

The table covers only three of the ten approved projects. It leaves out the rest. These are dated snapshots, so check newer releases before quoting them.

7.3 How fast was the CG project?

On 4 July 2026 Shri Ashwini Vaishnaw said the CG Semi plant went from groundbreaking to commercial production in just 27 months. He said the chips would serve automobiles, electric vehicles and consumer electronics.

He also said the chips would be exported to markets including Japan, the United States and Europe. These are his statements as PIB reported them.

7.4 What was the September 2025 milestone?

On 2 September 2025 PIB reported that the first set of Made-in-India chips from a pilot line was presented to the Prime Minister. PIB also says 20 chips designed and manufactured by Indian students at SCL were presented.

7.5 Is Micron's plant a fab?

No. PIB calls it an ATMP facility. That means assembly, test, marking and packaging. A fab makes the chip on a wafer. An ATMP plant finishes and packs chips. The second sentence is our own gloss.

8.1 What else supports chip design?

PIB’s backgrounder names several MeitY programmes that support design capability.

• Chips to Startup (C2S): launched in 2022 across 113 institutions. It has an outlay of Rs 250 crore for five years and aims to generate 85,000 industry-ready manpower.
• Design Linked Incentive (DLI): launched in 2021. It offers financial incentives and design infrastructure support. MeitY’s annual report gives its outlay as Rs 1000 crore.
• INUP-i2i: gives researchers, students and startups access to national nanofabrication facilities. PIB says more than 8000 skilled people have been trained.

8.2 Why do these programmes matter for DIR-V?

A chip design needs engineers, tools and a path to fabrication. These programmes supply the first two. PIB links DHRUV64 to DIR-V, C2S, ISM, DLI and INUP-i2i together. The first sentence is our own reading.

9.1 What was the third symposium?

IIT Madras’s press release of 22 July 2026 said it would host the third Digital India RISC-V Symposium on 1-2 August 2026. It named the venue as IIT Madras Research Park in Chennai.

The release said IIT Madras was partnering with MeitY and RISC-V International. It said the programme would feature the DIR-V Grand Challenge Hackathon.

9.2 What was on the agenda?

The event site lists two panel discussions. One is on security in the age of RISC-V. The other asks whether RISC-V can help solve India’s AI challenges.

It also lists sponsor keynote sessions. One of them names CDAC and Incore Semiconductors, with two other firms.

9.3 Why do the sources give two themes?

The press release names the theme as Empowering Bharat’s Semiconductor Future. The event site names the theme as Security for India’s digital future.

We found no source that settles which wording is official. Both pages are pre-event pages. We found no retrospective report, so this lesson does not describe what happened at the sessions.

10.1 Which mix-ups does this topic invite?

• Programme versus chip: DIR-V is a programme. DHRUV64, THEJAS32 and THEJAS64 are chips.
• The fabs: THEJAS32 was made at Silterra, Malaysia. THEJAS64 was made at SCL, named Mohali by PIB and Chandigarh by C-DAC.
• Different firsts: PIB calls DHRUV64 the first homegrown 1.0 GHz, 64-bit dual-core microprocessor. PIB also calls SHAKTI India’s first indigenous microprocessor. Attribute each claim to its own source.
• Design versus fabrication: DIR-V and C-DAC design chips. The India Semiconductor Mission supports plants such as Micron’s ATMP unit and the Dholera fab.
• The date trap: DIR-V was announced on 27 April 2022. The India Semiconductor Mission was launched in December 2021.
• SHAKTI and DIR-V: SHAKTI is IIT Madras’s family and is backed under DIR-V. The three DIR-V chips are VEGA-based.

10.2 Quick Q&A